The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through an underlying channel between the source and drain regions.
Magnetic random access memory (MRAM) is a non-volatile computer memory technology based on magnetoresistance. MRAM differs from volatile random access memory (RAM) in several respects. Because MRAM is non-volatile, MRAM can maintain memory content when the memory device is not powered. Though non-volatile RAM is typically slower than volatile RAM, MRAM has read and write response times that are comparable to that of volatile RAM. Unlike typical RAM technologies that store data as electric charge, MRAM data is stored by magnetoresistive elements. Generally, the magnetoresistive elements are made from two magnetic layers, each of which holds a magnetization. The two magnetic layers are separated from one another by a barrier layer. Together, the two magnetic layers and the barrier layer are referred to as a “magnetic tunnel junction stack” (“MTJ stack”). The magnetization of one of the magnetic layers (the “pinned layer” or “fixed layer”) is fixed in its magnetic orientation, and the magnetization of the other layer (the “free layer”) can be changed by an external magnetic field generated by a programming current. Thus, the magnetic field of the programming current can cause the magnetic orientations of the two magnetic layers to be either parallel, giving a lower electrical resistance across the layers (“0” state), or antiparallel, giving a higher electrical resistance across the layers (“1” state). The switching of the magnetic orientation of the free layer and the resulting high or low resistance states across the magnetic layers provide for the write and read operations of the typical MRAM cell.
Presently-known MRAM structures and methods for fabricating such structures all suffer from several drawbacks. For example, the prior art has experienced difficulties in embedding an MRAM structure into sub-100 nanometer (nm) complementary MOS (CMOS) logic devices with common back-end-of-line (BEOL) interconnects, such as contacts, insulators, metal levels, bonding sites for chip-to-package connections, etc., without substantially impacting yield and reliability. That is, subsequent to performing an etching process used to form the two magnetic layers and the barrier layer, sidewalls of the MTJ stack are exposed. The MTJ stack, having exposed sidewalls, may be damaged during BEOL processing. Furthermore, mobile ions and other contaminants related to the MTJ stack etching process may degrade BEOL inter-level dielectrics (ILDs). Integration is particularly challenging when the MTJ stack is disposed with fine-pitch interconnects (e.g., to achieve smaller memory cells) in conjunction with the ILDs common to sub-100 nm CMOS devices.
Accordingly, it would be desirable to provide integrated circuits and methods for fabricating integrated circuits with MRAM structures that are not susceptible (or are less susceptible) to damage during common BEOL processes. Additionally, it would be desirable to provide integrated circuits and methods for fabricating integrated circuits with MRAM structures that are able to be integrated with fine-pitch (e.g., sub-100 nm) CMOS devices. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.